In order to maintain and operate a communications system efficiently and effectively, the performance and operability of its components and subsystems should be tested and measured before being integrated into the system. One measure of the performance and operability of components and subsystems is a measurement of a bit error rate (BER). Bit error rate testers (BERTs) are designed specifically to test components and subsystems of digital communications systems.
The term “device under test” (DUT) referred to hereinafter is to be understood to mean a component or a subsystem or a grouping thereof which may comprise either optical or electrical subparts or any combination thereof. To be a compatible DUT for BER testing, the DUT must be designed to output the same data pattern it receives irrespective of what happens to the data pattern inside the DUT.
The rate of bits incorrectly conveyed through a DUT is a measure of the bit error rate of that device, and is an indication of the performance and operability of the device.
Referring to FIGS. 1A, and 1B, the operation of standard bit error rate testing arrangements is described. Referring first to FIG. 1A, a standard BER testing arrangement using an electrical signal, is described. A BERT 100 is connected by an output 102 and an input 104 to an input 122 and an output 124 respectively of a DUT 120. The BERT 100 has a Programmable Pattern Generator (PPG) 110, which produces a known test pattern at an output 112, which is connected to the output 102 of the BERT 100. The PPG 110 also outputs a separate clock signal at clock output 114 at a selected data rate. The known test pattern, which is typically a pseudo random binary sequence (PRBS), is injected into the DUT 120 at the selected data rate. The input 104 of the BERT 100 is connected to an input 132 of an Error Detector (ED) 130 of the BERT 100. The Error Detector 130 has its own pattern generator which produces an exact replica of the known test pattern produced by the PPG 110, and also has a comparator. The comparator of the ED 130 checks every bit received at the BERT input 104 from the DUT 120 against the known pattern internally generated by the ED 130. Each time the received bit differs from the known transmitted bit an error is logged. The PPG 110 and the ED 130, are made to operate at identical clock rates with a stable phase relationship between them by using the clock output 114 of the PPG 110 to trigger the ED 130 at clock input 133. The PPG clock 114 can effectively trigger the ED 130 only when the BERT 100 and the DUT 120 are in close proximity. When they are physically separated, for example at opposite ends of a transmission link, the PPG clock might not be in phase with the transmitted data, in which case the PPG clock 114 would not be able to trigger the ED 130. In this case the ED 130 should be triggered by a recovered clock obtained directly from the data itself.
In order to set up a BER testing arrangement for optical signals additional components are required. Referring to FIG. 1B, a BER testing arrangement using optical signals is described. The output 112 of the PPG 110, is connected to an electrical input 141 of a modulator 140 which modulates a CW laser source 143. An optical signal output from an optical output 142 of the modulator 140 passes through an optical output 102 of the BERT 100 over an optical fiber 144 to an optical input 122 of an optical DUT 120. An optical output 124 of the DUT 120 is connected by an optical fiber 145, through an optical input 104 of the BERT 100 to an optical input 151 of an optical receiver 150. An electrical data output 152 and a recovered clock output 153 of the optical receiver 150 are connected respectively to the data input 132 and clock input 133 of the ED 130. As was the case for testing electrical devices, the Error Detector 130 generates an exact replica of the known test pattern produced by the PPG 110, and also has a comparator which checks every bit received at the BERT input 104 from the DUT 120 against the known pattern internally generated by the ED 130. Each time the received bit differs from the known transmitted bit an error is logged. The ED 130 is triggered by the recovered clock from clock output 153 of the optical receiver 150 which has been recovered directly from the data itself.
For both arrangements and in general when testing numerous optical and/or electrical components in a subsystem, testing typically is done systematically, each subsystem having its own BER characterized in isolation and then in combination with other components in a step by step manner.
In general, there are two common data formats for the transmission of high-speed digital data, Non-Return to Zero (NRZ) signal format and Return to Zero (RZ) signal format. Non-Return to Zero (NRZ) signal format is the more popular of the two formats due to its inherent simplicity. In this particular format, each “0” or “1” data bit is represented by a low or high signal level, respectively, lasting an entire clock period. However, with ever-increasing data rates, especially in optical transmission systems, Return-to-Zero (RZ) signal formats are becoming the transmission format of choice. In RZ modulation format, each data bit occupies only a portion of the clock period creating a distinct transition between adjacent bits and, thereby, producing a cleaner optical signal for the receiver to read. For high-rate (>10 Gbps) or ultra-long-haul (>1000 km) transmission, the RZ modulation technique is now coming into vogue as it affords certain efficiency gains such as higher signal-to-noise ratio (SNR) and lower crosstalk amongst adjacent bits. RZ encoding also offers better immunity to fiber nonlinear effects and the effects of polarization mode dispersion (PMD), factors which can limit long-haul or high-rate transmission severely. Given the rising importance and popularity of this data format, components and subsystems designed to work with optical RZ signals should be BER tested with appropriate optical RZ signals.
In modern digital communications, data signals are being used at higher and higher data rates. Because of the physical constraints of systems in the electrical domain, it is often, if not always the case, that in the optical domain higher data rate components and subsystems are achieved before corresponding electrical components and subsystems are achieved. In order to test optical systems at data rates higher than that generally achievable in the electrical domain the use of optical multiplexers to achieve the desired rate for testing the high data rate optical DUT would be required. The use of optical demultiplexers would also be required to reduce the data rate coming back from the high data rate optical DUT to a manageable level. Current BER testers do not incorporate optical multiplexers to produce high data rate PRBSs and optical demultiplexers to reduce the data rate of the test to a level which can be processed by an electrical based error detector. Testing a modern digital communications systems with components or subsystems in both the optical and electrical domains, and having both high optically achievable data rates and data rates achievable in the electrical domain, would require multiple BERTs, and custom set-up of optical apparatus to add high rate optical functionality. To design and set-up such a cutting edge custom built set-up could be extremely difficult and time consuming. Such a time sensitive task as BER testing critical components of a communications system could therefore become expensive, and inefficient. It would be desirable for there to be a multi-purpose bit error rate tester which is capable of bit error rate testing both in the optical and the electrical domain. Moreover it would also be desirable if the bit error rate tester could perform BER tests at higher than the achievable rates in the electric domain, so that cutting edge optical components and subsystems could be tested without the need to set up custom testing apparatus.